In testing semiconductor IC devices by a semiconductor test system, such as an IC tester, a semiconductor IC device to be tested is provided with test signals at its appropriate pins at predetermined test timings defined relative to a tester rate or a previous timing signal. The IC tester receives output signals from the IC device under test generated in response to the test signals. The output signals are strobed, i.e., sampled, with a predetermined timing relationship or delay times with reference to the tester rate, and are compared with expected data to determine whether the IC device functions correctly.
Timing signals for producing various timings of the tester rate, test signals, and strobe signals are basically generated by a highly stabilized reference clock oscillator such as a crystal oscillator provided in the IC tester. When the required timing resolution in an IC tester is equal to or an integer multiple of the highest clock rate (shortest clock cycle) of a reference clock oscillator, timing signals can be generated by simply dividing the reference clock by a counter or a divider and synchronizing the divided output with the reference clock.
However, the modern IC testers are required to have timing resolution higher than the highest clock rate, i.e., the shortest time period, of a reference clock oscillator. For example, in the case where a clock rate of a reference clock oscillator available in the market is 10 ns (nanosecond), but an IC tester may need to have timing resolution of 0.1 ns such as a tester rate of 32.5 ns, a delay timing of 6.2 ns with reference to the start of the test rate, and the like. Furthermore, the modern IC testers dynamically change such timings in a cycle by cycle basis based on a test program.
To generate such timing signals with the timing resolution higher than the reference clock rate, it is known in the prior art that a combination of a counter and an accumulator can be used. In such an arrangement, high resolution timing signals which vary cycle by cycle can be generated based on the test program.
FIG. 10 is a block diagram showing an example of conventional semiconductor test system with an emphasis on a timing generator having such a combination of the counter and accumulator for generating the high resolution timing signals. The timing generator is generally formed of a rate generator 2 and a plurality of delay generators 3. A pattern generator 1 provides address data to write or read the timing data therein for generating timing signals. Although not shown, the pattern generator 1 also generates pattern data to determine a type of test signal and expected data to compare with resultant output signals from the device under test.
In the timing generator of FIG. 10, the rate generator 2 is to produce a rate signal (hereinafter "tester rate RA") which define a time length of each test cycle. The rate generator 2 is also to produce interpolation data RMD indicating a time length smaller than one reference clock period. Based on the tester rate RA and the interpolation data RMD, the delay generators 3 generate timing signals which define various timings within each tester rate RA such as timings of test signals (clocks) and strobe signals. Typically, such timing signals are defined by delay times relative to the start timing of the tester rate RA.
The rate generator 2 provides a tester rate RA and interpolation data RMD to the delay generator 3. The delay generator 3 combines delay times defined by the interpolation data RMD with the tester rate RA. The delay generator 3 further combines delay times defined by timing data stored in a timing memory therein. The test signals whose timings are thus determined by the delay generator 3 is wave-shaped by a wave formatter 38 and is applied to an IC device 4 to be tested. A pin electronics 39 interfaces the test signals through the wave formatter 38 with each pin of the IC device 4 to be tested. In an actual IC tester, a large number of delay generators 3 are prepared corresponding to the number of input/output pins of the IC device 4 to be tested.
The more detailed explanation of the conventional timing generator will be made with reference to FIGS. 10-12. The rate generator 2 includes a rate memory 21, an accumulator 22, registers 23 and 24, a counter 25, and a delay circuit 26. A reference oscillator 20 is also shown in the rate generator although it can be arranged in anywhere in the IC tester. The reference oscillator 20 oscillates at a frequency f.sub.HZ, for example 100 M.sub.HZ, which is a reference clock Ck and is used throughout the timing generator and other blocks of the IC tester. The rate memory 21 stores timing data which defines timings of a tester rate RA and interpolation data RMD for each test cycle. The timing data is formed through a software process based on types of test and IC devices to be tested as well as other factors.
The counter 25 receives data I in the timing data which is larger than and an integer multiple of the reference clock period T (=1/f.sub.HZ) of the reference clock Ck. The accumulator 22 receives a part of the rate data (fractional data) F which shows a time length smaller than the reference clock period T. The accumulator 22 adds interpolation data RMD in the previous cycle of the reference clock Ck provided from the register 23 to the fractional data F from the rate memory 21. For example, in the case where the desired timing for this cycle is 32.5 ns (nanosecond) relative to the previous timing, and the reference clock period is 10 ns, the data 30 ns (or simply 3 which is an integer multiple of 10 ns) is provided to the counter 25 and the fractional data 2.5 ns is provided to the accumulator 22.
The counter 25 counts the number of pulses of the reference clock Ck. When the counted value coincides with the data from the rate memory, the counter 25 generates a coincidence signal. Thus, in the above example, when the data indicating 30 nanosecond is received by the counter 25, the counter 25 seeks the coincidence of the reference clock with the data from the memory 21 by counting the number of reference clock pulses. When counting three clock pulses, the counter 25 generates a coincidence signal which is provided to the delay circuit 26.
The accumulator 22 outputs a carry signal when the accumulated data exceeds the reference clock period T, which is 10 ns in the above example. The carry signal is provided to the delay circuit 26 through the register 24. When the accumulated data does not exceed the reference clock period T, the resultant data is further added to the fractional data F from the rate memory 21 in the next cycle of the reference clock Ck. This process of accumulation is repeated throughout the generation of the timing signals in the IC tester.
When the carry signal is received from the accumulator 22 via the register 24, the delay circuit 26 produces a tester rate RA at the timing of the reference clock Ck coming immediately after the coincidence signal. Thus, every time the carry is generated by the accumulator, the delay circuit provides one cycle delay to the coincidence signal from the counter 25. The tester rate RA is supplied to the delay generator 3 to initiate the operation of the delay generator 3. The tester rate RA is also provided to the pattern generator 1 to access the next address of the rate memory 21. Further, in addition to the tester rate RA, the interpolation data RMD from the register 23 is received by the delay generator 3.
As noted above, a carry signal is not generated until the accumulated value in the accumulator 22 is reached the reference clock period T. Thus, so long as the carry signal is not received from the accumulator, the output of the counter 25 (coincidence signal) is transferred to the delay generator 3 as the tester rate RA. ***Thus, in this example, each period of the tester rates RA has a time length which is an integer multiple of the reference clock T.
As shown in FIG. 10, the delay generator 3 has a structure similar to the rate generator 2. The delay generator 3 includes a timing memory 31, an accumulator 32, registers 33 and 34, a counter 35, a delay circuit 36 and a variable delay circuit 37. The reference clock Ck is given to these circuit elements of the delay generator 3 to synchronize overall operations in the IC tester. The timing memory 31 stores timing data to determine the timings such as test signals and strobe signals with reference to the tester rate RA and the interpolation data RMD from the rate generator 2. The timing data for the timing memory 31 is formed through the software process similar to the rate memory 21 as noted above.
The counter 35 receives data I2 of the timing data from the timing memory 31 which is larger than and an integer multiple of the reference clock period T (=1/f.sub.HZ) of the reference clock Ck in the manner same as the counter 25 in the rate generator 2. The accumulator 32 receives fractional data F2 in the timing data which is smaller than the reference clock period T. Similar to the rate generator 2, in the case where the desired timing of, for example a strobe signal or a test clock signal in a test cycle is 32.5 ns, and the reference clock period is 10 ns, the data 30 ns is provided to the counter 35 and the fractional data 2.5 ns is provided to the accumulator 32.
The counter 35 is, for example, counts the number of pulses of the reference clock Ck. When the counted value coincides with the data from the timing memory 31, the counter 35 generates a coincidence signal. Thus, when the data indicating 30 ns is received from the data memory 31, the counter 35 generates a coincidence signal when counting three pulses of the reference clock CK having 10 ns clock period. The coincidence signal is provided to the delay circuit 36. The accumulator 32 outputs a carry signal when the accumulated data exceeds the reference clock period T, 10 ns in this example. The carry signal is provided to the delay circuit 36 through the register 34.
When the carry signal is received, the delay circuit 36 provides a delay time which is equal to one cycle of the reference clock Ck to the coincidence signal. Thus, every time the carry signal is generated by the accumulator 32, the delay circuit 36 provides one clock cycle delay to the coincidence signal from the counter 35. The carry signal is not generated until the accumulated value in the accumulator 32 is reached the reference clock period T. Thus, when there is no carry signal, the output (coincidence signal) of the counter 35 is transferred from the delay circuit 36 to the variable delay circuit 37 without additional delay.
The output signal from the delay circuit 36 is provided with an additional delay time by the variable delay circuit 37. The delay time by the variable delay circuit 37 is determined by the variable delay data which is a sum of the fractional data from the timing memory 31 and the interpolation data RMD from the rate generator 2. The variable data is provided from the accumulator 32 and the register 33 to the variable delay circuit 37.
In the timing generator, a plurality of delay generators 3 are provided each of which is assigned to a test signal or strobe signal corresponding to a pin of the IC device under test. The test signal whose timing is thus determined by the delay generator 3 is wave shaped by the wave formatter 38 and is applied to the IC device 4 under test. The pin electronics 39 interfaces the test signal from the wave formatter 38 with the corresponding input/output pin of the IC device 4 under test.
Referring to FIGS. 11-13, the operation of the timing generator of FIG. 10 is explained for a case of generating a plurality of timing signals for IC testing. In this example, it is assumed that signals with timings shown in FIGS. 11A-11C are to be generated for testing an IC device. Test signals (or clock signals) CLK1 and CLK2 are to be supplied to the IC device under test while a strobe signal STRB is used for sampling the resultant output signal from the IC device under test. The timing relationship between the test signals CLK1, CLK2 and STRB are also illustrated in FIGS. 11A-11C, respectively. In this example, it is also assumed that the time period of the reference clock Ck is 10 nanosecond.
As noted above, a plurality of delay circuits 3 are used in the timing generator. To generate these timing signals of FIG. 11, with the use of the timing generator of FIG. 10, the test signal CLK1 is assigned to a delay generator 3.sub.1, and the test signal CLK2 is assigned to a delay generator 3.sub.2, and the strobe signal STRB is assigned to a delay generator 3.sub.3. In this setting, each memory in the timing generator stores the timing data as shown in FIG. 12. The rate memory 21 is a memory in the rate generator 2 and the timing memories 31.sub.1 -31.sub.3 are memories correspond provided in the timing generators 3.sub.1 -3.sub.3. The address data is provided to the rate memory 21 and to the timing memories 31.sub.1 -31.sub.3 in the order of #0, #1, #2 . . . as shown in FIG. 12.
Since the test signal CLK1 is a reference for the other timings in this example, the rate memory 21 is provided with the timing data of 35 ns, 38 ns and 30 ns for the addresses #0, #1 and #2, respectively. The timing memory 31.sub.1 for generating the test signal CLK1 stores the timing data of 0 ns, 0 ns and 0 ns, with respect to the addresses #0, #1, #2. The timing memory 31.sub.2 for generating the test signal CLK2 stores the timing data of 7 ns, 5 ns, and 8 ns for the respective addresses of #0, #1, and #2. The timing memory 31.sub.3 for generating the strobe signal STRB stores the timing data 30 ns, 15 ns and 22 ns, respectively. As noted above, the fractional data F for the accumulator 22 in the rate generator 2 is 5 ns, 8 ns and 0 ns, respectively, which are differences among the integer multiple of the reference clock period 10 ns and the timing data in the rate memory 21.
FIGS. 13-17 are timing charts showing operations in the rate generator 2 and delay generators 3.sub.1 -3.sub.3 for generating the test signals CLK1, CLK2 and strobe signal STRB with the timings of FIG. 11. FIGS. 13A-13D are timing charts of the rate generator 2, FIGS. 14A-14E, 15A-15E, 16A-16E are timing charts of the delay generators 3.sub.1 -3.sub.3, respectively. The rate memory 21 and the timing memories 31.sub.1 -31.sub.3 store the timing data as noted above through a software process.
As shown in FIG. 13A, the time period T of the reference clock Ck is 10 ns. The counter 25 in the rate generator 2 receives the data from the rate memory 21 and counts the reference clock Ck. The data in this case is 30 ns and thus, when counting three pulses, the counter 25 outputs a coincidence signal for every 30 ns as shown in FIG. 13B. Because the accumulator 22 generates a carry, when accumulating the fraction data 5 ns and 8 ns, the delay circuit 26 generates the tester rate RA which is one clock cycle delayed by the reference clock period T as shown in FIG. 13C. Thus, the tester rate RA in this example shows 30 ns for the test first cycle and 40 ns for the next test cycle.
The interpolation data RMD in the second cycle of FIG. 13D indicates 5 ns since the fractional data of 5 ns is provided through the accumulator 22 and the register 23 which is delayed by one cycle. In the second cycle, the next fraction data of 8 ns is accumulated by the previous RMD of 5 ns which is returned from the register 23. Thus, the accumulator 22 generates the carry indicating 10 ns as noted above, and the remainder data of 3 ns is provided as the interpolation data RMD at the output of the register 23. In this manner, the interpolation data RMD is dynamically changed in each clock cycle by the accumulator 22 based on the fractional data in the rate memory 21.
The tester rate RA is received by the delay generator 3.sub.1 through the counter 35 as shown in FIG. 14A. As noted above with reference to FIG. 12, the timing memory 31.sub.1 stores the timing data indicating 0 ns, 0 ns and 0 ns for the respective three cycles as shown in FIG. 14B. There is no carry signal is generated by the accumulator 32, because the accumulation of the timing data and the interpolation data RMD in this situation will not exceed the reference clock period 10 ns. Thus, the delay circuit 36 outputs a signal having the same timing relationship as the tester rate received by the counter 35 as shown in FIG. 14C.
The output of the delay circuit 36 is received by the variable delay circuit 37 which is controlled by delay data from the register 33. Since the timing data stored in the timing memory 31 is 0 ns for three test cycles as above, the output of the accumulator 32 is unchanged from the interpolation data RMD, which is transferred to the register 33 in the next clock cycle. Therefore, the delay data from the register 33 shown FIG. 14D is the same data as the interpolation data RMD of FIG. 13D.
The variable delay circuit 37 adds a high resolution delay time based on the delay data from the register 33 to the output of the delay circuit 36. For the first test cycle, the delay time 5 ns is added to the second pulse, and for the second test cycle, the delay time 3 ns is added to the third pulse. As a result, the test signal CLK1 as shown in FIG. 14E is generated by the delay generator 3.sub.1.
In the similar manner, the tester rate RA is received by the delay generator 3.sub.2 from the counter 25 of the rate generator 2 as shown in FIG. 15A. As noted with reference to FIG. 12, the timing memory 31.sub.2 stores the timing data indicating 7 ns, 5 ns and 8 ns for the respective three cycles as shown in FIG. 15B. A carry signal is not generated by the accumulator 32 for the first test cycle since accumulation of the interpolation data RMD is 0 ns, i.e., the sum of the data RMD and the timing data 7 ns will not exceed the reference clock period 10 ns. Thus, the accumulator 32 provides the delay data to the register 33 without change. The register 33 transfers the data indicating 7 ns to the variable delay circuit 37 in synchronism with the next reference clock Ck as shown in FIG. 15D.
In the second cycle, since the accumulation of the timing data 5 ns and the interpolation data RMD of 5 ns results in 10 ns, the accumulator 32 produces a carry signal which is supplied to the delay circuit 36 through the register 34. Thus, second pulse from the delay circuit 36 is delayed by one reference clock cycle, i.e., 10 ns, as shown in FIG. 15C. The delay data from the register 33 indicates 0 ns as shown in FIG. 15D, which is supplied to the variable delay circuit 37.
Similarly, in the next test cycle, the timing data of 8 ns and the RMD 3 ns are added which exceeds the reference clock period 10 ns. Thus, a carry signal is generated which again delays the third pulse from the delay circuit 36 by one clock cycle. The delay data from the register 33 indicates 1 ns which is a difference between 11 ns (8 ns plus 3 ns) and the reference clock period 10 ns, and is provided to the variable delay circuit 37 as shown in FIG. 15D.
The output of the delay circuit 36 is received by the variable delay circuit 37 which is controlled by the delay data from the register 33. Since the delay data from the register 33 is 7 ns in the first test cycle, the delay time 7 ns is added to the first pulse from the delay circuit 36 which results in the first pulse of the test signal CLK2 of FIG. 15E. For the next pulse, the delay time is 0 ns. For the third pulse, the delay time 1 ns is added by the variable delay circuit 37. Thus, the test signal CLK2 is generated as shown in FIG. 15E.
Regarding the strobe signal STRB, the tester rate RA is received by the delay generator 3.sub.2 from the counter 25 of the rate generator 2 as shown in FIG. 16A. As noted above with reference to FIG. 12, the timing memory 31.sub.3 stores the timing data indicating 30 ns, 15 ns and 22 ns for the respective three cycles as shown in FIG. 16B. Since the timing data of 30 ns is greater than the reference clock period 10 ns, the data 30 ns is given to the counter 35 which down counts the number of reference clock Ck.
Thus, the output of the counter 35 is delayed by 30 ns for the first pulse which is transferred at the output of the delay circuit 36 as shown in FIG. 16C. For the second pulse, the timing data of 10 ns is provided to the counter 35 while the fractional data of 5 ns is provided to the accumulator 22. Thus, the counter 35 generates its output signal which is delayed by 10 ns from the second pulse of tester rate RA. The fractional data 5 ns is accumulated with the RMD data 5 ns by the accumulator 32 which produces a carry signal. The carry signal from the register 34 further causes one cycle delay in the delay circuit 36, i.e., an overall delay of 20 ns from the second pulse of the tester rate RA as shown in FIG. 16C.
For the third pulse, the timing data 20 ns is provided to the counter 35 and the fraction data 2 ns is provided to the accumulator 22. Thus, the third pulse from the delay circuit 36 is delayed by 20 ns and the delay data which is the sum of the RMD data 3 ns and the fraction data 2 ns is produced at the output of the register 33 as shown in FIG. 16D. The strobe signal STRB is generated by combining the delay time from the register 33 with the output signal from the delay circuit 36 as shown in FIG. 16E.
FIGS. 17A-17K are timing charts showing the more details of the operation of the rate generator 2 many aspects of which are the same as that shown in the timing charts of FIGS. 13A-13D. The reference clock Ck in FIG. 17A has the time period of 10 ns. The rate memory 21 stores the rate data 35 ns, 38 ns and 30 ns for the first three test cycles as shown in FIG. 17B which is also listed in FIG. 12. The rate memory 21 stores the rate data 35 ns, 38 ns and 30 ns for the first three cycle in FIG. 17B and the counter 25 is provided with data indicating 30 ns or three counts for each test cycle as in FIG. 17C. Thus, the counter 25 down counts the reference clock Ck in FIG. 17D and generates the coincidence signal for every 30 ns as in FIG. 17E.
The fractional data F in this situation is 5 ns, 8 ns, and 0 ns as in FIG. 17F which is applied to the accumulator 22 from the rate memory 21. In the first test cycle, since the fractional data is less than the reference time period T (10 ns), the carry signal is not generated by the accumulator 22. Thus, the fractional data 5 ns at the output of the accumulator 22 as shown in FIG. 17G is provided at the output of the register 23 in the next clock cycle as in FIG. 17H.
In the second test cycle, the accumulator 22 receives the fractional data 8 ns which is added to the interpolation data 5 ns returned from the register 23. Thus, the accumulated result is 13 ns which exceeds the reference 10 ns period. The accumulator 22 generates a carry signal which is received by the delay circuit 26 through the register 24 in the next clock cycle as in FIG. 17I. Also in the next cycle, the remainder data indicating 3 ns is transferred from the accumulator 22 to the register 23 as in FIG. 17G.
The delay circuit 26 outputs the input signal from the counter 26 with the same timing as the tester rate RA in synchronism with the reference clock Ck. When receiving the carry signal from the register 24, the delay circuit 26 provides a 10 ns delay to the input (coincidence) signal so that the tester rate RA expanded by 10 ns for the corresponding test cycle.
Thus, as shown in FIG. 17J, in the first test cycle, the time interval of the tester rate RA is 30 ns while in the second test cycle, the time interval is 40 ns because of the carry from the accumulator 22. The interpolation data RMD is produced at the register 23 as shown in FIG. 17K. As in the example of FIGS. 13-16, the tester rate RA and the interpolation data RMD are supplied to the delay generators 3.sub.1 -3.sub.3 to form the required test signals and strobe signals.
FIG. 18 shows another example of circuit configuration for forming a timing generator of the kind of FIG. 10 based on the accumulator and the counter. The timing data greater than the reference clock period T is provided to a counter 125 while the fractional data smaller than the reference clock period T is provided to an accumulator 122. When the fractional data accumulated to the previous data returned from a register 123 is greater than the reference clock period T, for example 10 ns, the accumulator 122 provides a carry signal to the counter 125.
When receiving the carry signal, the counter 125 holds the operation for the corresponding reference cycle. The output of the counter 125 is received by a variable delay circuit 137 wherein a delay time defined by the delay data from the register 123 is added to the counter output provided through a coincidence detector 126. The output signal of the variable delay circuit 137 is used as a test signal or a strobe signal as described above.
In the conventional timing generators as described above, however, are not able to generate the same timing signals when the reference clock period is changed. When the reference clock is changed, the data stored in the rate memory or the timing memory has to be changed accordingly by modifying a test program. In other words, in the conventional timing generator, the software (test program) cannot be compatible when the frequency of the reference oscillator is changed. Such a need of the frequency change in the reference clock arises, for example, when two or more IC testers having different reference frequencies one another are to be used in a parallel fashion while using the same timing signals.
In the timing generators as shown in FIGS. 10 or 18, the weight of the data to be supplied to the counters and the accumulators varies with the change of the reference frequency. Thus, it is not possible to generate the same timing signals for the new reference frequency without changing the timing data to be stored in the rate memory or timing memories. Namely, if the reference frequency or period has been changed from Tn to Tm, the rate data and the timing data for the reference period Tm have to be changed from that of the reference period Tn for the ratio expressed by Tn/Tm. This means that the test program cannot be compatible in this situation, since the rate data and timing data are included in the existing test program.